Low or medium efficiency solar cells need to be produced in a very efficient way in order to keep the overall costs as low as possible. Such low cost solar cells are typically manufactured in a continuous high throughput production line, in which handling of wafers must be kept to a minimum. The number of process steps should be as low as possible and the process steps must preferably allow such continuous processing without interruption. Examples of such processes are given in European Patent Application No. 979546694 entitled “Semiconductor device with two selectively diffused regions” and in U.S. Pat. No. 5,726,065 entitled “Method of Preparing Solar Cells Front Contacts”.
The “front end” process of preparing a solar cell comprises the steps of (see FIG. 1): providing a starting semiconductor substrate, typically a low cost substrate (1), such as a polycrystalline or multicrystalline p-type silicon wafer (FIG. 1a); substrate cleaning between different steps; surface texturing, e.g., using wet chemicals to roughen the front surface (2) of the substrate (FIG. 1b) as disclosed e.g. in European Publication EP-773590-A1 entitled “Solar cell comprising multicrystalline silicon and method of texturing the surface of P-type multicrystalline silicon”; forming the emitter region (3) (FIG. 1c), as, e.g., described in European Application No. 979546694 entitled “Semiconductor device with two selectively diffused regions”, by phosphorus solid source doping of the wafer in a furnace to form the emitter region (3) and furnace diffusion of the phosphorus dopants; and etching the phosphorus oxide or phosphorus glass formed during the previous phosphorus solid source doping.
The substrate is doped in all surfaces that are exposed to the gaseous environment. Not only the front, but also the edges, openings in the substrate, and the uncovered areas of the back side of the wafer will be doped.
The “back end” process of preparing a solar cell comprises the steps of (see FIG. 1): forming contacts (4) to the emitter (3), e.g. by screen printing on the front side (2) a paste comprising metal particles and using a thermal step to sinter these metal particles to the semiconductor substrate, such as in the firing step as disclosed, e.g., in U.S. Pat. No. 5,698,451 (FIG. 1d); forming contacts (5) at the back side (6) of the bulk region (7) which is of a conductivity type, e.g., p-type, opposite to the emitter dopant type, e.g., n-type. This can also be done by the screen-printing and firing technique used for the emitter contacts (FIG. 1e).
The firing step of the emitter-contacts (4) and the back-contacts (5) can be done simultaneously.
A significant problem arising from continuous high throughput solar cell processes is the isolation of the n-type emitter (3) and the p-type collector bulk contacts so that no electrical short circuit of the diode occurs. In order to avoid the shunting or short-circuiting of the emitter contacts (4) to the bulk contacts (5), no overlap (9) or direct electrical contact between the n-type emitter region (3) and the bulk contacts (5) is allowed. Various methods are employed to prevent such overlap, and some of these methods are presented below. These methods can be categorized into patterned methods and unpatterned methods, depending upon whether the separation of the both regions is adjustable, i.e., layout dependent, or fixed, i.e., done by employing a given toolset.
Examples of such patterned methods include the following. During the step of doping the emitter, the bulk contact region is masked (8) with a given overlap over the bulk contact region (5) and this part of the surface remains p-type doped (see FIG. 2a). This masking material needs to be removed without affecting the solar cell. Such an approach is disclosed in European Application No. 979546694 entitled “Semiconductor device with two selectively diffused regions.”
During the emitter doping step the perimeter of the bulk contact region (5) is masked (8). The bulk region itself, however, will be n-type doped. During subsequent processing of the bulk contacts, counter-doping is needed, e.g., by the diffusing or alloying with the metal paste, to compensate for this n-type doping within area bordered by the masking perimeter and to convert the contact region (5) into a p-type doped region (see FIG. 2b). This masking material needs to be removed without affecting the solar cell.
Instead of masking the perimeter (8) of the bulk contact region, as disclosed above, a paste can be dispensed as shown in FIG. 2d. This paste (11) can electrically isolate the back side contact (5) from the emitter regions (3) in three ways. During subsequent processing, the paste (11) reduces the dopant level of the emitter region underneath the dispensed ring (11). This reduction can occur, e.g., by removing the n-type dopants in the emitter region located underneath the paste area (11). The paste can, e.g., dissolve the semiconductor material of the substrate underneath it, whereby the dopants present in this affected region have a different solubility in the dissolved material at the given process temperature than at the temperature at which they were introduced earlier in the process. The excess dopants can be absorbed by the paste material. Such a method is disclosed in European Application No. 56169378, which discloses using a paste that melts the silicon; during subsequent processing the paste (11) counter-dopes the emitter regions underneath the dispensed ring. By alloying the substrate underneath with dopants present in the paste (11), a p-type region is formed extending from the back surface (6) throughout the emitter region (3) to the bulk region (7). Such a method is disclosed in Japanese Application No. 5619378, which discloses using an aluminum-based paste for counter-doping.
Examples of unpatterned methods include the following. In “High throughput laser isolation of crystalline silicon solar cells” by G. Emanuel, 17th European Photovoltaic Solar Energy Conference and Exhibition, Munich, Germany 22–26, Oct. 2001, application of laser technology to isolate the edges of solar cells was described. The laser scribing evaporates the substrate material on the back surface and hence a groove is formed separating the n-doped surface regions from the contact regions to the p-doped bulk. Sometimes the edges (10) of the wafers are removed. In “A new passivation method for edge shunts of silicon solar cells” by M. Al-Rifai et al., 17th European Photovoltaic Solar Energy Conference and Exhibition, Munich, Germany 22–26, Oct. 2001, a method is described wherein wafers are first stacked. On the edges of this wafer stack, a KOH aqueous solution is applied by means of a sponge. Then, the wafer stack with the wetted edges is heated up until the reaction temperature of the KOH solution is reached. At this temperature the KOH starts to etch the silicon, thereby removing n-type doped edge regions. A device prepared according to this method is shown in FIG. 2c. A disadvantage of this technique is that the stacked wafers vary in size, typically by about 0.5 mm, and hence not only the edges but also the front and/or back surfaces of the substrate are etched, resulting in a smaller active area. Stacked wafers also need additional wafer handling that can cause damage to the substrate surface. The time between applying the KOH aqueous solution and etching the edges should be limited as much as possible to make sure that the etching liquid remains on the substrate and to avoid drying out or evaporating the etching liquid. This disadvantage is related to the fact that an etching liquid can not be confined to a given area.
In U.S. Pat. No. 5,894,853 (Fujisaki Tatsuo et al.), U.S. Pat. No. 5,688,366 (Ichinose Hirofumi et al.), U.S. Pat. No. 6,388,187 (Kusakari Masayuki et al.) and U.S. Pat. No. 5,296,043 (Kawakami Soichiro et al.), etching pastes are disclosed for etching transparent conducting films, for example, Indium Tin Oxide (ITO). ITO is considered as a conductive compound and is not considered in the art as a semiconductor substrate such as silicon or germanium.